64k x 16 static ram cy7c1021bnv33 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06433 rev. ** revised february 1, 2006 features ? 3.3v operation (3.0v?3.6v) ?high speed ?t aa = 10, 12, 15 ns ? cmos for optimum speed/power ? low active power (l version) ? 576 mw (max.) ? low cmos standby power (l version) ? 1.80 mw (max.) ? automatic power-down when deselected ? independent control of upper and lower bits ? available in 44-pin tsop ii and 400-mil soj ? available in a 48-ball mini bga package functional description [1] the cy7c1021bnv is a high-performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power-down feature that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 9 through i/o 16 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 1 to i/o 8 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 9 to i/o 16 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 1 through i/o 16 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1021bnv is available in 400-mil-wide soj, standard 44-pin tsop type ii, and 48-ball mini bga packages. we logic block diagram pin configurations 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view soj / tsop ii 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 16 a 2 ce i/o 3 i/o 1 i/o 2 bhe nc a 1 a 0 18 17 20 19 i/o 4 27 28 25 26 22 21 23 24 nc v ss i/o 7 i/o 5 i/o 6 i/o 8 a 6 a 7 ble v cc i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 a 8 a 9 a 10 a 11 64k x 16 ram array i/o 1 ?i/o 8 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 512 x 2048 sense amps data in drivers oe a 2 a 1 i/o 9 ?i/o 16 ce we ble bhe a 8 note: 1. for guidelines on sram system design, please refer to the ?s ystem design guidelines? cypress application note, available on t he internet at www.cypress.com [+] feedback [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. ** page 2 of 10 pin configurations selection guide -10 -12 -15 maximum access time (ns) 10 12 15 maximum operating current (ma) commercial 160 150 140 industrial 180 170 160 maximum cmos standby current (ma) commercial/industrial 5 5 5 l0.5 0.5 0.5 mini bga (top view) ble oe bhe we a 0 a 4 a 1 a 2 ce v ss i/o 1 a 3 i/o 9 i/o 11 i/o 10 a 6 a 5 i/o 3 i/o 2 i/o 5 i/o 12 nc a 7 i/o 4 v cc nc v ss v cc i/o 13 nc nc i/o 15 i/o 14 i/o 8 a 8 a 15 a 14 i/o 6 i/o 7 i/o 16 nc a 12 a 13 nc nc a 9 a 10 a 11 1234 5 6 a b c d e f g h [+] feedback [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. ** page 3 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v cc to relative gnd [1] .... ?0.5v to +4.6v dc voltage applied to outputs in high z state [1] ......................................?0.5v to v cc +0.5v dc input voltage [1] .................................. ?0.5v to v cc +0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current ..................................................... >200 ma operating range range ambient temperature v cc commercial 0c to +70c 3.3v 10% industrial ?40c to +85c 3.3v 10% electrical characteristics over the operating range parameter description test conditions -10 -12 -15 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc +0.3v 2.2 v cc +0.3v 2.2 v cc +0.3v v v il input low voltage [1] ? 0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input load current gnd < v i < v cc ? 1+1 ?1 +1 ?1 +1 a i oz output leakage current gnd < v i < v cc , output disabled ? 1+1 ?1 +1 ?1 +1 a i cc v cc operating supply current v cc = max., i out =0ma f = f max = 1/t rc com?l 160 150 140 ma ind?l 120 170 160 ma i sb1 automatic ce powerdown current ?ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 40 40 40 ma i sb2 automatic ce power down current ?cmos inputs max. v cc , ce > v cc ?0.3v, v in > v cc ?0.3v or v in < 0.3v, f = 0 5 5 5 ma l500 500 500 a capacitance [2] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz 6 pf c out output capacitance 8 pf ac test loads and waveforms note: 1. minimum voltage is ?2.0v for pulse durations of less than 20 ns. 2. tested initially and after any design or proce ss changes that may affect these parameters. 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 30 pf including jig and scope 3.3v output 5 pf including jig and scope (a) (b) output r 317 ? r 317 ? r2 351 ? r2 351 ? 167 equivalent to: thvenin equivalent 1.73v 30 pf rise time: 1 v/ns fall time: 1 v/ns [+] feedback [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. ** page 4 of 10 switching characteristics [3] over the operating range parameter description -10 -12 -15 unit min. max. min. max. min. max. read cycle t rc read cycle time 10 12 15 ns t aa address to data valid 10 12 15 ns t oha data hold from address change 3 3 3 ns t ace ce low to data valid 10 12 15 ns t doe oe low to data valid 4 6 7 ns t lzoe oe low to low z 0 0 0 ns t hzoe oe high to high z [4, 5] 5 6 7 ns t lzce ce low to low z [5] 3 3 3 ns t hzce ce high to high z [4, 5] 5 6 7 ns t pu ce low to power-up 0 0 0 ns t pd ce high to power-down 12 12 15 ns t dbe byte enable to data valid 5 6 7 ns t lzbe byte enable to low z 0 0 0 ns t hzbe byte disable to high z 5 6 7 ns write cycle [6] t wc write cycle time 10 12 15 ns t sce ce low to write end 8 9 10 ns t aw address set-up to write end 7 8 10 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 8 8 10 ns t sd data set-up to write end 6 6 8 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low z [5] 3 3 3 ns t hzwe we low to high z [4, 5] 5 6 7 ns t bw byte enable to end of write 8 8 9 ns data retention characteristics over the operating range (l version only) parameter description conditions [7] min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current com?l v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 100 a t cdr [8] chip deselect to data retention time 0 ns t r [9] operation recovery time t rc ns notes: 3. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 4. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 5. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 6. the internal write time of the memory is defined by the overlap of ce low, we low and bhe / ble low. ce , we and bhe / ble must be low to initiate a write, and the transition of these signals can terminate the wr ite. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 7. no input may exceed v cc + 0.5v. 8. tested initially and after any design or process changes that may affect these parameters. 9. t r < 3 ns for the -12 and -15 speeds. t r < 5 ns for the -20 and slower speeds. [+] feedback [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. ** page 5 of 10 data retention waveform 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc switching waveforms read cycle no. 1 [10, 11] read cycle no. 2 (oe controlled) [11, 12] notes: 10. device is continuously selected. oe , ce , bhe and/or bhe = v il . 11. we is high for read cycle. 12. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current i cc i sb [+] feedback [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. ** page 6 of 10 write cycle no. 1 (ce controlled) [13, 14] write cycle no. 2 (ble or bhe controlled) notes: 13. data i/o is high impedance if oe or bhe and/or ble = v ih . 14. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble t t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce [+] feedback [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. ** page 7 of 10 write cycle no. 2 (we controlled, oe low) truth table ce oe we ble bhe i/o 1 ?i/o 8 i/o 9 ?i/o 16 mode power h x x x x high z high z power-down standby (i sb ) l l h l l data out data out read - all bits active (i cc ) l h data out high z read - lower bits only active (i cc ) h l high z data out read - upper bits only active (i cc ) l x l l l data in data in write - all bits active (i cc ) l h data in high z write - lower bits only active (i cc ) h l high z data in write - upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) l x x h h high z high z selected, outputs disabled active (i cc ) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe [+] feedback [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. ** page 8 of 10 ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1021bnv33l-10vxc 51-85082 44-lead (400-mil) molded soj (pb-free) commercial CY7C1021BNV33L-10ZXC 51-85087 44-lead tsop type ii (pb-free) 12 cy7c1021bnv33l-12zc 51-85087 44-lead tsop type ii cy7c1021bnv33l-12zxc 51-85087 44-lead tsop type ii (pb-free) 15 cy7c1021bnv33l-15zc 51-85087 44-lead tsop type ii cy7c1021bnv33l-15zxc 51-85087 44-lead tsop type ii (pb-free) cy7c1021bnv33l-15vxc 51-85082 44-lead (400-mil) molded soj (pb-free) cy7c1021bnv33l-15bai 51-85096 48-ball mini ball grid array (7 mm x 7 mm) industrial cy7c1021bnv33l-15vxi 51-85082 44-lead (400-mil) molded soj (pb-free) cy7c1021bnv33l-15zxi 51-85087 44-lead tsop type ii (pb-free) cy7c1021bnv33l-15zi 51-85087 44-lead tsop type ii please contact local sales representative regarding availability of these parts. package diagrams g f e d c b a 5 64321 pin 1 corner 5.25 3.75 0.75 0.75 ?0.300.05(48x) ?0.25 m c a b 0.15(4x) 0.210.05 1.20 max. seating plane 0.530.05 0.25 c 0.10 c h e h f g a b c d 6 5 12 3 4 pin 1 corner top view bottom view 7.000.10 7.000.10 a b ?0.05 m c (laser mark) b a c 7.000.10 7.000.10 1.875 2.625 0.36 48-ball fbga (7 mm x 7 mm x 1.2 mm) (51-85096) 51-85096-*f [+] feedback [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. ** page 9 of 10 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all product and company names mentio ned in this document may be the tr ademarks of their respective holders. package diagrams (continued) 44-lead (400-mil) molded soj (51-85082) 51-85082-*b 44-pin tsop type ii (51-85087) 51-85087-*a [+] feedback [+] feedback
cy7c1021bnv33 document #: 001-06433 rev. ** page 10 of 10 document history page document title: cy7c1021bnv33 64k x 16 static ram document number: 001-06433 rev. ecn no. issue date orig. of change description of change ** 423847 see ecn nxr new data sheet [+] feedback [+] feedback
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